Sense amplification circuits, output circuits, nonvolatile memory devices, memory systems, memory cards having the same, and data outputting methods thereof

ABSTRACT

An output circuit of a nonvolatile memory device includes a sense amplification circuit configured to, during a sensing operation, generate output data based on a comparison between a first voltage on a data line and a reference voltage on a reference data line during a sensing operation, the first voltage corresponding to data read from at least one memory cell, and the sense amplification circuit being further configured to connect the reference data line with a ground terminal during the sensing operation.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of and claims priority under 35U.S.C. §120 to U.S. application Ser. No. 13/427,019, filed Mar. 22,2012, which claims the benefit of U.S. Provisional Application No.61/466,538, filed Mar. 23, 2011, and which claims priority under 35U.S.C §119 to Korean Patent Application No. 10-2011-0042986, filed May6, 2011, the entire contents of each of which are incorporated herein byreference.

BACKGROUND

1. Field

Example embodiments relate to amplification circuits, output circuitshaving the same, nonvolatile memory devices, memory systems, memorycards, and/or data outputting methods thereof.

2. Description of Conventional Art

Semiconductor memory devices are microelectronic components commonlyfound in digital logic systems, such as computers, andmicroprocessor-based applications ranging from satellites to consumerelectronics. Therefore, advances in the fabrication of semiconductormemory devices, including process enhancements andcircuit-design-related developments that allow scaling to higher memorydensities and faster operating speeds, help establish performancestandards for other digital logic families.

Semiconductor memory devices generally include volatile memory devicesand non-volatile memory devices. Non-volatile memories are capable ofstoring data even when the power is turned off. Non-volatile memory datastorage modes include permanent and reprogrammable modes. Non-volatilememories are commonly used for program and microcode storage in a widevariety of applications including, for example, computers, avionics,telecommunications, and consumer electronics.

A typical example of a non-volatile memory device is a flash memorydevice. Recently, multi-bit memory devices storing multi-bit data in amemory cell are becoming more common as demand for higher densities ofmemory devices increases.

SUMMARY

At least some example embodiments provide nonvolatile memory devicescapable of performing relatively high speed data output operations.

At least some example embodiments provide nonvolatile memory devicescapable of reducing layout area.

At least one example embodiment provides an output circuit including:page buffer latches configured to latch data read from memory cells; subdata lines configured to receive voltages corresponding to the latcheddata in response to latch addresses; a data line connected with the subdata lines during a sensing operation; a reference data line to which acurrent path is formed during the sensing operation; and a senseamplification circuit configured to differentially sense the referencedata line and the data line, and to output data corresponding to thesensing result, during the sensing operation.

At least one other example embodiment provides an output circuitincluding: a plurality of page buffer latches configured to latch dataread from a plurality of memory cells; a plurality of sub data linesconfigured to receive voltages corresponding to the latched data inresponse to latch addresses; a data line connected to the plurality ofsub data lines; a reference data line to which a current path is formedduring a sensing operation; and a sense amplification circuit configuredto, during the sensing operation, sense a voltage difference between thereference data line and the data line, and to output data correspondingto the sensed voltage difference.

According to at least some example embodiments, the output circuit mayfurther include: a column selection circuit configured to connect thedata line with the sub data lines sequentially in response to columnaddresses. The column selection circuit may include: a plurality ofcolumn selection transistors. Each of the plurality of column selectiontransistors may be configured to connect a sub data line from among thesub data lines with the data line in response to a column address fromamong the column addresses.

The reference data line may be coupled to a load element having a loadcorresponding to a load of the data line.

According to at least some example embodiments, the sense amplificationcircuit may include: a pre-charger configured to pre-charge thereference data line and the data line; a current path generatorconfigured to form the current path to the reference data line after thereference data line and the data line are pre-charged; and adifferential sense amplifier configured to sense a voltage differencebetween the reference data line and the data line.

The pre-charger may include at least one transistor configured to applya power supply voltage to the reference data line and the data line inresponse to a pre-charge signal.

The current path generator may electrically connect the reference dataline to a ground terminal during the sensing operation. The current pathgenerator may change a voltage of the reference data line during thesensing operation.

When the current path generator lowers a voltage of the reference dataline during the sensing operation, a falling slope (rate of decrease) ofa voltage of the reference data line is slower than a falling slope(rate of decrease) of a voltage of the data line when the latched datais indicative of a decrease in the voltage of the data line.

A voltage variation of the reference data line may be less than that ofthe data line. For example, during the sensing operation, a voltagevariation in the voltage of the reference data line may be a valuebetween voltage values corresponding to the latched data.

According to at least some example embodiments, the current pathgenerator may include: at least one current path transistor connectedbetween the reference data line and a path node, the at least onecurrent path transistor having a gate configured to receive a trim code;and a path forming transistor configured to connect the path node with aground terminal in response to an inverted pre-charge signal. The trimcode may vary according to an address for determining a physicallocation of a page buffer. The trim code may be implemented by at leastone of an e-fuse, a laser fuse, and a register set.

The differential sense amplifier may include: a first transistorconnected between a power terminal and an output node, and having a gateconnected to an inverted output node; a second transistor connectedbetween the power terminal and the inverted output node, and having agate connected to the output node; a third transistor connected betweenthe output node and a bias node, and having a gate connected to theinverted output node; a fourth transistor connected between the invertedoutput node and the bias node, and having a gate connected to the outputnode; and a fifth transistor configured to connect the bias node and aground terminal during the sensing operation.

At least one other example embodiment provides a nonvolatile memorydevice including: a memory cell array including at least one memoryblock having memory cells connected with bit lines; page buffersconfigured to latch data read from memory cells corresponding to the bitlines, respectively; sub data lines configured to receive voltagescorresponding to data latched at the page buffers in response to latchaddresses, respectively; a column selection circuit configured toconnect the sub data lines with corresponding data lines in response tocolumn addresses; and an output driver configured to output data bysensing voltage differences between the data lines and correspondingreference data lines during a sensing operation, wherein a current pathis formed to each of the reference data lines during the sensingoperation.

At least one other example embodiment provides a nonvolatile memorydevice including: a memory cell array including at least one memoryblock having a plurality of memory cells, the plurality of memory cellsbeing connected to a plurality of bit lines; a plurality of page buffersconfigured to latch data read from the plurality of memory cells via theplurality of bit lines; a plurality of sub data lines configured toreceive a plurality of voltages corresponding to data latched at theplurality of page buffers in response to a plurality of latch addresses;a column selection circuit configured to connect the plurality of subdata lines with a corresponding plurality of data lines in response to aplurality of column addresses; and an output circuit configured tooutput data by sensing voltage differences between the plurality of datalines and a corresponding plurality of reference data lines during asensing operation, wherein a current path is formed to each of theplurality of reference data lines during the sensing operation.

According to at least some example embodiments, the at least one memoryblock may be configured to have an all bit line architecture or aneven-odd bit line architecture.

According to at least some example embodiments, each of the page buffersmay include a page buffer latch, wherein even or odd ones of the bitlines are connected to the page buffer latch, and the page buffer latchis configured to latch data read from a corresponding one of the memorycells during a read operation, or to latch data input from an externaldevice during a program operation.

According to at least some example embodiments, each page buffer mayinclude a first page buffer latch and a second page buffer latch. Thefirst page buffer latch may be connected to even ones of the bit lines,and configured to latch data read from a corresponding memory cell ofthe even bit lines during a read operation. The second page buffer latchmay be connected to odd ones of the bit lines, and configured to latchdata read from a corresponding memory cell of the odd bit lines duringthe read operation.

The sense amplification circuit may include: a pre-charger configured topre-charge the reference data lines and the data lines in response to apre-charge signal; a current path generator configured to generate acurrent flow to the reference data lines in response to an invertedpre-charge signal; and a differential sense amplifier configured tosense a voltage difference between the reference data lines and the datalines in response to a differential sense signal.

A read cycle for outputting data latched at each of the page buffers mayinclude: a pre-charge period in which the data lines and the referencedata lines are pre-charged; a develop period in which the page buffersare connected with corresponding ones of the data lines; and a senseperiod in which voltage differences between the developed data lines andthe reference data lines are sensed.

During the pre-charge period, a power supply voltage may be applied tothe reference data lines and the data lines in response to thepre-charge signal.

During the develop period, the sub data lines may be connected withcorresponding ones of the data lines in response to the columnaddresses, and the latched data of the page buffers may be transferredto corresponding ones of the sub data lines.

During the sense period, voltage differences between the data lines andcorresponding reference data lines may be sensed in response to adifferential sense signal.

The nonvolatile memory device may further include: an input/outputbuffer configured to temporarily store the data output from the senseamplification circuit or data input from an external device.

The nonvolatile memory device may further include: a randomizing circuitconfigured to randomize data input from an external device during aninput operation or to de-randomize the data output from the senseamplification circuit during an output operation.

At least one other example embodiment provides a data output method of anonvolatile memory device including: latching data of memory cells viacorresponding bit lines; transferring voltages corresponding to thelatched data to a data line; and sensing a voltage difference betweenthe data line and a reference data line, wherein the sensing includesforming a current path at the referenced data line.

At least one other example embodiment provides a data output method of anonvolatile memory device, the method including: latching data outputfrom a plurality of memory cells via a corresponding plurality of bitlines; transferring voltages corresponding to the latched data to a dataline; and sensing a voltage difference between the data line and areference data line, the sensing including forming a current path to thereference data line.

According to at least some example embodiments, the latching may includepre-charging the bit lines; and sensing voltage variations of thepre-charged bit lines.

At least one other example embodiment provides a memory systemincluding: a nonvolatile memory device; and a memory controllerconfigured to control the nonvolatile memory device. The nonvolatilememory device is configured to output data by: differentially sensingdata lines; and sequentially transferring voltages corresponding to readdata and form a current path to the reference data lines. The outputdata is provided to the memory controller.

At least one other example embodiment provides a memory systemincluding: a nonvolatile memory device; and a memory controllerconfigured to control the nonvolatile memory device. The nonvolatilememory device is configured to: during a sensing operation, read data bysensing a voltage difference between data lines and correspondingreference data lines, form a current path to the reference data lines,and output the read data to the memory controller.

At least one other example embodiment provides a sense amplificationcircuit including: a pre-charger configured to pre-charge a referencedata line and a data line in response to a pre-charge signal; a currentpath generator configured to form a current path at the reference dataline in response to an inverted version of the pre-charge signal; and adifferential sense amplifier configured to sense a voltage differencebetween the reference data line and the data line in response to asensing signal. During a sensing operation, data to be sensed istransferred to the pre-charge data line, and when a voltage of the dataline is lowered by the transferred data, a falling slope of a voltage ofthe reference data line is slower than that of the data line.

At least one other example embodiment provides a sense amplificationcircuit including: a pre-charger configured to pre-charge a referencedata line and a data line in response to a pre-charge signal; a currentpath generator configured to form a current path to the reference dataline in response to an inverted pre-charge signal; and a differentialsense amplifier configured to sense a voltage difference between thereference data line and the data line in response to a sensing signal.During a sensing operation, data to be sensed is transferred to the dataline, and when a voltage of the data line is lowered by the transferreddata, a rate of decrease of a voltage of the reference data line is lessthan a rate of decrease of a voltage of the data line.

At least one other example embodiment provides a data output method of anonvolatile memory device. According to at least this exampleembodiment, the method includes: transferring output data to a dataline; changing a voltage of a reference data line to generate areference voltage having a given, desired or predetermined slope; anddifferentially sensing a voltage difference between the referencevoltage and the data line.

At least one other example embodiment provides data output method of anonvolatile memory device. According to at least this exampleembodiment, the method includes: transferring output data to a dataline; changing a voltage of a reference data line to generate areference voltage having a first slope; and sensing a voltage differencebetween the data line and the reference data line.

According to at least some example embodiments, the data output methodmay further include: applying a pre-charge voltage to the data line andthe reference data line before transferring of output data to the dataline.

The voltage of the reference line may be changed such that a fallingslope (rate of decrease) of a voltage of the reference data line isslower than that of the data line when a voltage of the data line islowered by the output data.

The voltage of the reference data line may be changed such that a risingslope (rate of increase) of a voltage of the reference data line isslower than that of the data line when a voltage of the data line isincreased by the output data.

The sensing may include: discharging the data line and the referencedata line.

At least one other example embodiment provides a nonvolatile memorydevice including: a plurality of output units, wherein each of theplurality of output units includes page buffer latches configured tolatch data read from memory cells; sub data lines configured to receivevoltages corresponding to the latched data in response to latchaddresses; a data line connected with the sub data lines during asensing operation; a reference data line connected with at least onecurrent sink during the sensing operation; and a sense amplificationcircuit configured to differentially sense the reference data line andthe data line during the sensing operation, and to output datacorresponding to the sensing result.

At least one other example embodiment provides a nonvolatile memorydevice including: a plurality of output units, each of the plurality ofoutput units including: a plurality of page buffer latches configured tolatch data read from a plurality of memory cells; a plurality of subdata lines configured to receive a plurality of voltages correspondingto the latched data in response to a plurality of latch addresses; adata line connected with the plurality of sub data lines during asensing operation; a reference data line connected with at least onecurrent sink during the sensing operation; and a sense amplificationcircuit configured to sense a voltage difference between the referencedata line and the data line during the sensing operation. The senseamplification circuit is further configured to output data correspondingto the sensed voltage difference.

According to at least some example embodiments, data from each of theplurality of output units may be output to an external device via oneinput/output line. Data from at least two output units of the pluralityof output units may be output to an external device via an input/outputline.

According to at least some example embodiments, the nonvolatile memorydevice may further include: an input/output buffer configured to atleast one of output data from the sense amplification circuit to anexternal device, and receive data from the external device.

The input/output buffer may include: a first input/output bufferconfigured to operate in a single-ended transmission mode in response toa first transmission mode selection signal; and a second input/outputbuffer configured to operate in a differential transmission mode inresponse to a second transmission mode selection signal.

The nonvolatile memory device may further include: a transmission modeselector configured to generate the first and second transmission modeselection signals. The transmission mode selector may generate the firstand second transmission mode selection signals according to a userconfiguration or an e-fuse configuration.

At least one other example embodiment provides a memory card including:at least one nonvolatile memory device configured to store user data; abuffer memory device configured to temporarily store data generatedduring operation; and a memory controller configured to control the atleast one nonvolatile memory device and the buffer memory device. The atleast one nonvolatile memory device includes: page buffer latchesconfigured to latch data read from memory cells; sub data linesconfigured to receive voltages corresponding to the latched data inresponse to latch addresses; a data line connected with the sub datalines during a sensing operation; a reference data line connected withat least one current sink during the sensing operation; and a senseamplification circuit configured to differentially sense the referencedata line and the data line during the sensing operation, and to outputdata corresponding to the sensing result.

At least one other example embodiment provides a memory card including:at least one nonvolatile memory device configured to store user data; abuffer memory device configured to temporarily store generated data; anda memory controller configured to control the at least one nonvolatilememory device and the buffer memory device. The at least one nonvolatilememory device includes: a plurality of page buffer latches configured tolatch data read from a plurality of memory cells; a plurality of subdata lines configured to receive a plurality of voltages correspondingto the latched data in response to a plurality of latch addresses; adata line connected with the plurality of sub data lines during asensing operation; a reference data line connected with at least onecurrent sink during the sensing operation; and a sense amplificationcircuit configured to sense a voltage difference between the referencedata line and the data line during the sensing operation. The senseamplification circuit is further configured to output data correspondingto the sensed voltage difference.

At least one other example embodiment provides an output circuitincluding: a sense amplification circuit configured to, during a sensingoperation, generate output data based on a comparison between a firstvoltage on a data line and a reference voltage on a reference data lineduring a sensing operation, the first voltage corresponding to data readfrom at least one memory cell, and the sense amplification circuit beingfurther configured to connect the reference data line with a groundterminal during the sensing operation.

According to at least some example embodiments, the sense amplificationcircuit may generate the output data while the reference data line isconnected to the ground terminal.

The output circuit may further include: at least one page buffer latchconfigured to latch the data read from at least one memory cell; and/ora column selection circuit configured to connect the data line with theat least one page buffer in response to a column address signal.

The sense amplification circuit may include: a differential senseamplifier configured to, during the sensing operation, compare the firstvoltage and the reference voltage, and to generate the output data basedon the comparison; and a current path generating circuit configured toconnect the reference data line with the ground terminal during thesensing operation.

The sense amplification circuit may further include: a pre-chargecircuit configured to pre-charge the reference data line and the dataline in response to a pre-charge signal, wherein the current pathgenerating circuit connects the reference data line with the groundterminal based on a trim code and an inverted pre-charge signal.

BRIEF DESCRIPTION OF THE FIGURES

Example embodiments will become apparent from the following descriptionwith reference to the following figures, wherein like reference numeralsrefer to like parts throughout the various figures unless otherwisespecified, and wherein:

FIG. 1 is a block diagram illustrating a nonvolatile memory deviceaccording to an example embodiment of inventive concepts.

FIG. 2 is a diagram illustrating a memory block in FIG. 1 according toan example embodiment of inventive concepts.

FIG. 3 is a diagram illustrating a memory block in FIG. 1 according toanother example embodiment of inventive concepts.

FIG. 4 is a diagram for describing an output operation of a nonvolatilememory device in FIG. 1 according to an example embodiment of inventiveconcepts.

FIG. 5 is a diagram for describing an output operation of a nonvolatilememory device in FIG. 1 according to another example embodiment ofinventive concepts.

FIG. 6 is a diagram illustrating a pre-charger in FIG. 4 according to anexample embodiment of inventive concepts.

FIG. 7 is a diagram illustrating a current path generator 142 in FIG. 4according to an example embodiment of inventive concepts.

FIG. 8 is a timing diagram for describing example operation of a currentpath generator in FIG. 7.

FIG. 9 is a diagram illustrating a differential sense amplifier in FIG.4 according to an example embodiment of inventive concepts.

FIG. 10 is a timing diagram illustrating a data output operationaccording to an example embodiment of inventive concepts.

FIG. 11 is a diagram illustrating an output operation of a nonvolatilememory device in FIG. 1 according to another example embodiment ofinventive concepts.

FIG. 12 is a diagram illustrating an output operation of a nonvolatilememory device in FIG. 1 according to still another example embodiment ofinventive concepts.

FIG. 13 is a flowchart illustrating a data output method of anonvolatile memory device according to an example embodiment ofinventive concepts.

FIG. 14 is a diagram illustrating a nonvolatile memory device accordingto another example embodiment of inventive concepts.

FIG. 15 is a diagram illustrating a nonvolatile memory device accordingto still another example embodiment of inventive concepts.

FIG. 16 is a diagram showing a non-volatile memory device according tostill another example embodiment of inventive concepts.

FIG. 17 is a circuit diagram showing an equivalent circuit of one memoryblock of memory blocks illustrated in FIG. 16.

FIG. 18 is a diagram illustrating a memory system according to anexample embodiment of inventive concepts.

FIG. 19 is a block diagram of a memory card according to an exampleembodiment of inventive concepts.

FIG. 20 is a block diagram of a moviNAND according to an exampleembodiment of inventive concepts.

FIG. 21 is a block diagram of an SSD according to an example embodimentof inventive concepts.

FIG. 22 is a block diagram of a computing system including an SSD inFIG. 21 according to an example embodiment of inventive concepts.

FIG. 23 is a block diagram of an electronic device including an SSD inFIG. 21 according to an example embodiment of inventive concepts.

FIG. 24 is a block diagram of a server system including an SSD in FIG.21 according to an example embodiment of inventive concepts.

FIG. 25 is a diagram showing a handheld electronic device according toan example embodiment of inventive concepts.

DETAILED DESCRIPTION

Inventive concepts are described more fully hereinafter with referenceto the accompanying drawings, in which some example embodiments of theinventive concept are shown. Inventive concepts may, however, beembodied in many different forms and should not be construed as limitedto the example embodiments set forth herein. Rather, these exampleembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the inventive concepts tothose skilled in the art. In the drawings, the size and relative sizesof layers and regions may be exaggerated for clarity. Like numbers referto like elements throughout.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of inventive concepts.

Spatially relative terms, such as “beneath”, “below”, “lower”, “under”,“above”, “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. For example, if the device inthe figures is turned over, elements described as “below” or “beneath”or “under” other elements or features would then be oriented “above” theother elements or features. Thus, the exemplary terms “below” and“under” can encompass both an orientation of above and below. The devicemay be otherwise oriented (rotated 90 degrees or at other orientations)and the spatially relative descriptors used herein interpretedaccordingly. In addition, it will also be understood that when a layeris referred to as being “between” two layers, it can be the only layerbetween the two layers, or one or more intervening layers may also bepresent.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the inventiveconcept. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to”, “coupled to”, or “adjacent to” anotherelement or layer, it can be directly on, connected, coupled, or adjacentto the other element or layer, or intervening elements or layers may bepresent. In contrast, when an element is referred to as being “directlyon,” “directly connected to”, “directly coupled to”, or “immediatelyadjacent to” another element or layer, there are no intervening elementsor layers present.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which the inventive concepts belong. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and/orthe present specification and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

A nonvolatile memory device according to an example embodiment ofinventive concepts may be a NAND flash memory, a vertical NAND flashmemory, a NOR flash memory, a resistive random access memory (RRAM), aphase-change memory (PRAM), a magnetoresistive RAM (MRAM), aferroelectric RAM (FRAM), a spin transfer torque RAM (STT-RAM), or thelike. Below, for ease of description, a nonvolatile memory device may beassumed to be a NAND flash memory device.

FIG. 1 is a block diagram illustrating a nonvolatile memory deviceaccording to an example embodiment of inventive concepts.

Referring to FIG. 1, a nonvolatile memory device 100 may include amemory cell array 110, a page buffer circuit 120, a column selection(or, Y-selection) circuit 130, a sense amplification circuit 140, and aninput/output (I/O) buffer 150.

The memory cell array 110 may include a plurality of memory blocks MB0to MBi (i being a natural number). The plurality of memory blocks MB0 toMBi may share bit lines BL0 to BLn (n being a natural number). Each ofthe plurality of memory blocks MB0 to MBi may include a plurality ofmemory cells (not shown) for storing data.

The page buffer circuit 120 may read and store data from memory cellscorresponding to the bit lines BL0 to BLn in a selected one of thememory blocks MB0 to MBi at a read operation. The page buffer circuit120 may temporarily store input data at a program operation. Althoughnot shown in FIG. 1, the page buffer circuit 120 may include pagebuffers corresponding to the bit lines BL0 to BLn, respectively.

Each page buffer may include a plurality of latches (not shown). Herein,at least one (called a page buffer latch) of the plurality of latchesmay be connected with a sub data line SDL in response to a correspondinglatch address LA.

Although not shown in FIG. 1, each page buffer may include a pre-chargecircuit configured to pre-charge a corresponding bit line and a sensingcircuit configured to sense data from a memory cell connected with thecorresponding bit line. Herein, the sensing circuit may be a currentsensing circuit or a voltage sensing circuit.

A detailed description of an example page buffer circuit is disclosed inU.S. Pat. No. 7,379,333, the entirety of which is incorporated herein byreference.

The column selection circuit 130 may connect sub data lines SDL withcorresponding data lines DL in response to a column address YA.

The sense amplification circuit 140 may output plural data bits IO<7:0>by performing differential sensing with respect to data lines DL andreference data lines DLref. Herein, each reference data line DLref maybe coupled to an equivalent load 135. Herein, the equivalent load 135may have the same or substantially the same load as a load (e.g., thecolumn selection circuit 130, the sub data line SDL, etc.) connectedwith each data line DL. For example, the load may include a resistor, acapacitor, a reactor, etc.

In at least one example embodiment, each reference data line DLref maybe configured to have the same or substantially the same length as acorresponding data line DL.

The reference data lines DLref may form a current path by the senseamplification circuit 140 during a sensing operation. For ease ofdescription, forming a current path may mean that each reference dataline DLref is electrically connected with a ground terminal. If eachreference data line DLref is in a pre-charged state, its voltage maystart to lower because a current path is formed during a sensingoperation. In other words, each reference data line DLref may be loweredto a given, desired or predetermined voltage from a pre-charged voltageduring the sensing operation. Herein, the given, desired orpredetermined voltage may be about half the maximum value which avoltage of each reference data line DLref is capable of being loweredto. For example, each reference data line DLref may be lowered to aground voltage from a power supply voltage.

In another example embodiment, each reference data line DLref may beconnected electrically with a voltage terminal having a voltage higherthan a pre-charge voltage of the reference data lines DLref and the datalines DL during the sensing operation.

At a read operation, the input/output buffer 150 may receive dataIO<7:0> output from the sense amplification circuit 140 to output it toan external device. During a program operation, the input/output buffer150 may transfer data IO<7:0> input from the external device to thesense amplification circuit 140.

The nonvolatile memory device 100 according to an example embodiment ofinventive concepts may perform a high-speed data sensing operation bydifferentially sensing data.

Further, the nonvolatile memory device 100 according to an exampleembodiment of inventive concepts may reduce a layout area by performingdifferential sensing using reference data lines DLref connected with anequivalent load 135.

FIG. 2 is a diagram illustrating a memory block in FIG. 1 according toan example embodiment of inventive concepts.

Referring to FIG. 2, a memory block MBj (j being an integer between 0and i) may include a plurality of cell strings, each of which has astring selection transistor SST connected with a string selection lineSSL, a plurality of memory cells MC0 to MCm connected with a pluralityof word lines WL0 to WLm (m being a natural number), and a groundselection transistor GST connected with a ground selection line GSL.

Herein, the string selection transistor SST may be connected with acorresponding bit line, and the ground selection transistor GST may beconnected with a common source line CSL. The common source line CSL maybe biased by a ground voltage or a CSL voltage (e.g., a power supplyvoltage) from a CSL driver (not shown).

Each of the memory cells MC0 to MCm may store 1-bit data or multi-bitdata.

The memory block MBj in FIG. 2 may have an all bit line architecture. Inan example embodiment, all bit lines BL0 to BLn (n being a naturalnumber) may be selected at the same or substantially the same timeduring a read or program operation. However, there is no need to selectall bit lines at the same or substantially same time upon reading orprogramming.

Further description of an example all bit line architecture is disclosedin U.S. Pat. No. 7,379,333, the entirety of which is incorporated hereinby reference.

FIG. 3 is a diagram illustrating a memory block in FIG. 1 according toanother example embodiment of inventive concepts.

Referring to FIG. 3, a memory block MBj_1 (j being an integer between 0and i) may include even bit lines BLe0 to BLen and odd bit lines BLo0 toBLon. The memory block MBj_1 in FIG. 3 may be implemented to have aneven-odd bit line architecture. In an example embodiment, upon readingor programming, the even bit lines BLe0 to BLen may be firstly selectedand then the odd bit lines BLo0 to BLon may be selected. In anotherexample embodiment, upon reading or programming, the odd bit lines BLo0to BLon may be firstly selected and then the even bit lines BLe0 to BLenmay be selected.

Further description of an example even-odd bit line architecture isdisclosed in U.S. Pat. No. 7,379,333, the entirety of which isincorporated herein by reference.

FIG. 4 is a diagram for describing an example output operation of anonvolatile memory device in FIG. 1 according to an example embodimentof inventive concepts. For ease of description, a data sensing method ofan output operation (or, a read operation) will be described below. Atthe output operation a page buffer circuit 120, a column selectioncircuit 130, and a sense amplification circuit 140 may be referred to asan output circuit. Herein, the output circuit may include a plurality ofoutput units OPTU0 to OPTU7, each of which outputs data IO<i> (i beingan integer from 0 to 7) by performing differential sensing on data of apage buffer. Herein, the data IO<0> to IO<7> may be output to anexternal device via data lines.

For ease of description and example purposes, eight output units OPTU0to OPTU7 are illustrated in FIG. 4. However, it is well understood thatthere is no need to limit the number of output units.

Below, the first output unit OUTP0 will be more fully described.

A page buffer circuit unit 120_0 may include a plurality of page buffersPB0 to PBp+q (p and q being an integer of 1 or more). The page buffersPB0 to PBp+q may be connected with sub data lines SDL0 to SDLr (r beingan integer of 1 or more) by a given, desired or predetermined unit. Forexample, page buffers PB0 to PBp may be connected with a sub data lineSDL0, and page buffers PBq to PBp+q may be connected with a sub dataline SDLr. A page buffer circuit 120 in FIG. 1 may be formed of aplurality of page buffer circuit units.

Each of the page buffers PB0 to PBp+q may include a page buffer latchCLAT and NMOS transistors NM1 and NM2. For ease of description, a pagebuffer PB0 connected with a bit line BL0 will be described more fully.One end of the page buffer latch CLAT may be connected with the bit lineBL0 in response to a bit line selection signal BLS, and the other endthereof may be connected with a gate of the NMOS transistor NM1. TheNMOS transistors NM1 and NM2 may be connected in series between a groundterminal and the sub data line SDL0. A gate of the NMOS transistor NM2may be connected to receive a latch address LA<0>. Data of the pagebuffer latch CLAT may be sent to the sub data line SDL0 in response tothe latch address LA<0>.

In FIG. 4, for ease of description, there is exemplarily illustrated thecase that each of the page buffers PB0 to PBp+q includes one cache latchCLAT (hereinafter, referred to as a page buffer latch). Although notshown in drawing, each of the page buffers PB0 to PBp+q according to anexample embodiment of inventive concepts may further include a pluralityof latches other than the page buffer latch CLAT.

A column selection circuit unit 130_0 may include a plurality of columnselection transistors YST0 to YSTr. The column selection transistorsYST0 to YSTr may be connected between corresponding sub data lines SDL0to SDLr and the data line DL0, respectively. Herein, gates of the columnselection transistors YST0 to YSTr may be connected to receivecorresponding column addresses YA<0> to YA<r>, respectively. Sub datalines SDL0 to SDLr may be sequentially connected with the data line DL0in response to the column addresses YA<0> to YA<r>.

A sense amplification circuit unit 140_0 may include a pre-charger 141,a current path generator 142, and a differential sense amplifier 143.The sense amplification circuit unit 140_0 may output data IO<0> bydifferentially sensing data latched at the page buffers PB0 to PBp+q inresponse to a differential sensing signal DSS. Herein, the data IO<0>may be output to an external device via a corresponding IO data line. Asense amplification circuit 140 in FIG. 1 may include a plurality ofsense amplification circuit units.

The pre-charger 141 may be connected between a data line DL0 and areference data line DLref0. When data latched at the page buffers PB0 toPBp+q is sensed, the pre-charger 141 may pre-charge the data line DL0and the reference data line DLref0 in response to a pre-charge signalPS. In an example embodiment, the data line DL0 and the reference dataline DLref0 may be pre-charged to a power supply voltage.

In an example embodiment, the reference data line DLref0 may beconnected with an equivalent load 135_0. Herein, the equivalent load135_0 may be configured to correspond to a load connected with the dataline DL0. In an example embodiment, the equivalent load 135_0 may beimplemented by a transistor as illustrated in FIG. 4.

The current path generator 142 may provide a current path to thereference data line DLref0 upon sensing of the data lines DL0 andDLref0. The current path generator 142 may be in an inactive state whenthe reference data line DLref0 and the data line DL0 are pre-charged andin an active state when data of the data line DL0 is sensed. That is,the current path generator 142 may interrupt a current path of thereference data line DLref0 when the data lines DL0 and DLref0 arepre-charged and may form a current path of the reference data lineDLref0 pre-charged during a sensing operation.

In particular, the current path generator 142 may form a current pathsuch that a ratio of a voltage variation of the data line DL0 to avoltage variation of the reference data line DLref0 is maintained with agiven, desired or predetermined value during a sensing operation. Forexample, the current path generator 142 may be implemented such that avoltage variation of the reference data line DLref0 becomes less thanthat of the data line DL0. In particular, a voltage variation of thereference data line DLref0 may be about half a voltage variation of thedata line DL0. That is, the current path generator 142 may beimplemented such that a voltage variation is generated according to thefollowing equation.

V _(DLref)=(V _(DL) _(_) _(max) +V _(DL) _(_) _(min))/2  (1)

In the equation 1, V_(DLref) may be a voltage variation of the referencedata line DLref0, V_(DL) _(_) _(max) may be a maximum voltage of thedata line DL0, and V_(DL) _(_) _(min) may be a minimum voltage of thedata line DL0.

The current path generator 142 may constantly vary (increase ordecrease) a voltage of the reference data line DLref0 regardless of avoltage of the data line DL0 (or, data latched at the page buffers PB0to PBp+q). That is, the current path generator 142 may lower a voltageof the reference data line DLref0 regardless of a voltage of the dataline DL0 during a sensing operation.

In an example embodiment, the current path generator 142 may be formedof at least one current sink activated during a sensing operation.

In another example embodiment, the current path generator 142 may beformed of at least one current source activated during a sensingoperation.

The differential sense amplifier 143 may perform differential sensing onthe data line DL0 and the reference data line DLref0 in response to thedifferential sense signal DSS. That is, during a sensing operation, thedifferential sense amplifier 143 may judge or determine whether latcheddata is ‘0’ or ‘1’, by sensing a voltage difference between a loweredvoltage of the reference data line DLref0 and a voltage of the data lineDL0. A detailed description of an example of the differential senseamplifier 143 is disclosed in U.S. Pat. No. 6,574,129, the entirety ofwhich is incorporated herein by reference.

The output unit OPTU0 is described in detail herein. However, remainingoutput units OPTU1 to OPTU7 may be configured to have the same orsubstantially the same function and/or operation as that describedabove. Each of the output units OPTU0 to OPTU7 may output data byperforming differential sensing on one data line and one reference dataline.

In FIG. 4, data to be output to one IO data line may be output from eachof the output units OPTU0 to OPTU7. However, inventive concepts are notlimited thereto. Data to be output to one IO data line may be outputfrom at least two output units.

FIG. 5 is a diagram for describing example output operation of anonvolatile memory device in FIG. 1 according to another exampleembodiment of inventive concepts.

Referring to FIG. 5, output units OPTU0 to OPTUt (t being a naturalnumber) may output data to be output to one IO line IO<i>. Herein, theoutput unit OPTU0 may be the same or substantially the same as that inFIG. 4, and thus, description thereof is omitted.

FIG. 6 is a diagram illustrating a pre-charger in FIG. 4 according to anexample embodiment of inventive concepts.

Referring to FIG. 6, a pre-charger 141 may include PMOS transistors PM1,PM2, and PM3. The PMOS transistor PM1 may be connected between a powerterminal VDD and a data line DL0, the PMOS transistor PM2 may beconnected between the power terminal VDD and a reference data lineDLref0, and the PMOS transistor PM3 may be connected between the dataline DL0 and the reference data line DLref0. Gates of the PMOStransistors PM1 to PM3 may be connected to receive a pre-charge signalPS. The pre-charger 141 may apply a power supply voltage to the dataline DL0 and the reference data line DLref0 in response to thepre-charge signal PS.

FIG. 7 is a diagram illustrating a current path generator 142 in FIG. 4according to an example embodiment of inventive concepts.

Referring to FIG. 7, a current path generator 142 may include aplurality of current path transistors CPT0 to CPTs and a pass formingtransistor PDT. The current path transistors CPT0 to CPTs may beconnected in parallel between a reference data line DLref0 and a pathnode ND. Herein, gates of the current path transistors CPT0 to CPTs maybe connected to receive corresponding trim codes TRM<0> to TRM<s>,respectively.

In an example embodiment, the trim codes TRM<0> to TRM<s> may be fixed.

In another example embodiment, the trim codes TRM<0> to TRM<s> may bevariable. For example, the trim codes TRM<0> to TRM<s> may be variedaccording to an address for selecting a memory block. Further, the trimcodes TRM<0> to TRM<s> may be varied according to an address fordetermining a physical location of a page buffer.

In an example embodiment, the trim codes TRM<0> to TRM<s> may be formedof at least one of an e-fuse, a laser fuse, an anti-fuse, and a registerset.

The path forming transistor PDT may be connected between the path nodeND and a ground terminal. Herein, a gate of the path forming transistorPDT may be connected to receive a pre-charge signal PS. That is, thepath forming transistor PDT may be turned on in response to thepre-charge signal PS. For example, when the pre-charge signal PS is at alow level, the path forming transistor PDT may be turned off. When thepre-charge signal PS is at a high level, the path forming transistor PDTmay be turned on.

When the path forming transistor PDT is turned on (or, when thepre-charge signal PS is at a high level), the current path generator 142may provide a current path to the reference data line DLref0 in responseto the trim codes TRM<0> to TRM<s>.

The current path generator 142 in FIG. 7 may be a type of current sink.Herein, the current sink may be activated in response to the pre-chargesignal PS.

The current path generator 142 in FIG. 7 may include a plurality ofcurrent path transistors CPT0 to CPTs. However, it is well understoodthat the current path generator is not limited to include a plurality ofcurrent path transistors. The current path generator 142 according to anexample embodiment of inventive concepts may be configured to include atleast one current path transistor.

FIG. 8 is a timing diagram for describing example operation of a currentpath generator in FIG. 7.

Referring to FIG. 8, when a pre-charge signal PS is at a low level, nocurrent flows to a reference data line DLref0. When the pre-chargesignal PS is at a high level, a current flows to the reference data lineDLref0.

FIG. 9 is a diagram illustrating a differential sense amplifier in FIG.4 according to an example embodiment of inventive concepts.

Referring to FIG. 9, a differential sense amplifier 143 may include PMOStransistors P1 and P2, NMOS transistors N1 to N3, and transmission gatesTG1 and TG2.

The PMOS transistor P1 may be connected between a power terminal VDD anda data node DN, and the PMOS transistor P2 may be connected between thepower terminal VDD and an inverted data node DNb. A gate of the PMOStransistor P1 may be connected with the inverted data node DNb, and agate of the PMOS transistor P2 may be connected with the data node DN.Data IO<0> may be output from the data node DN. Alternatively, dataIO<0> may be output from the inverted data node DNb.

The NMOS transistor N1 may be connected between the data node DN and abias node BN, the NMOS transistor N2 may be connected between theinverted data node DNb and the bias node BN, and the NMOS transistor N3may be connected between the bias node BN and a ground terminal. A gateof the NMOS transistor N1 may be connected with the inverted data nodeDNb, a gate of the NMOS transistor N2 may be connected with the datanode DN, and a gate of the NMOS transistor N3 may be connected toreceive a differential sense signal DSS.

The transmission gate TG1 may connect a data line DL0 with the data nodeDN in response to the differential sense signal DSS, and thetransmission gate TG2 may connect a reference data line DLref0 with theinverted data node DNb in response to the differential sense signal DSS.

The differential sense amplifier 143 may sense a voltage differencebetween the data line DL0 and the reference data line DLref0 in responseto the differential sense signal DSS, and may output the sensed resultas data.

FIG. 10 is a timing diagram illustrating a data output operationaccording to an example embodiment of inventive concepts. FIG. 10 showsan example operation of outputting data latched at the first and secondpage buffers PB0 and PB1. Referring to FIGS. 4 to 9, a read cycle periodt0 may be divided into a pre-charge period t1, a develop period t2, anda sense period t3. In an example embodiment, the pre-charge period t1may be about 5 ns, the develop period t2 may be about 3 ns, and thesense period t3 may be about 2 ns. However, times corresponding to theperiods t1, t2, and t3 are not limited thereto.

First, an operation of outputting data latched at a page buffer latchCLAT of the first page buffer PB0 will be described.

During the pre-charge period t1, data lines DL0 and DLref0 may bepre-charged in response to a low level of a pre-charge signal PS.Herein, the data lines DL0 and DLref0 may be pre-charged with a powersupply voltage.

During the develop period t2, the first latch address LA<0> and thefirst column address YA<0> may have a high level. The page buffer latchCLAT of the first page buffer PB0 may be connected with a sub data lineSDL0 in response to the high level of the first latch address LA<0>. Avoltage corresponding to data latched at the page buffer latch CLAT ofthe first page buffer PB0 may be applied to the sub data line SDL0.Below, for ease of description, it is assumed that data latched at thepage buffer latch CLAT of the first page buffer PB0 is ‘1’ and a voltagecorresponding to the data ‘1’ is a ground voltage.

Further, the sub data line SDL0 may be connected with a data line DL0 inresponse to the high level of the column address YA<0>. Since a voltageof the sub data line SDL0 is a ground voltage and a voltage of the dataline DL0 is a power supply voltage, a voltage of the data line DL0 maystart to lower. At the same or substantially the same time, since acurrent path is formed at a reference data line DLref0, a voltage of thereference data line DLref0 may lower. Since half a current flowing tothe data line DL0 flows to the reference data line DLref0, a fallingslope of a voltage of the reference data line DLref0 may be slower thanthat of the data line DL0. Accordingly, during the develop period t2, avoltage of the reference data line DLref0 may be higher than that of thedata line DL0. That is, a difference Vdiff of a voltage of the referencedata line DLref0 minus a voltage of the data line DL0 may be a positivevoltage.

During the sense period t3, the first latch address LA<0> and the firstcolumn address YA<0> may have a high level, and the data sense signalDSS may have a high level. The differential sense amplifier 143 maysense a voltage difference Vdiff between the reference data line DLref0and the data line DL0 in response to a high level of the data sensesignal DSS. At this time, since the voltage difference Vdiff is apositive voltage, a voltage (e.g., a ground voltage) corresponding todata ‘1’ may be output to the data node DN.

Afterwards, data latched at a page buffer latch CLAT of the second pagebuffer PB1 may be output in a manner similar or substantially similar tothat described above.

At the pre-charge period t1, the data lines DL0 and DLref0 may bepre-charged in response to a low level of the pre-charge signal PS.Herein, the data lines DL0 and DLref0 may be pre-charged with a powersupply voltage.

During the develop period t2, the second latch address LA<1> and thefirst column address YA<0> may have a high level.

The page buffer latch CLAT of the second page buffer PB1 may beconnected with the sub data line SDL0 in response to the high level ofthe second latch address LA<1>. A voltage corresponding to data latchedat the page buffer latch CLAT of the second page buffer PB1 may beapplied to the sub data line SDL0. Below, for ease of description, it isassumed that data latched at the page buffer latch CLAT of the secondpage buffer PB1 is ‘0’ and a voltage corresponding to the data ‘0’ is apower supply voltage.

Further, the sub data line SDL0 may be connected with a data line DL0 inresponse to the high level of the column address YA<0>. Since a voltageof the sub data line SDL0 is a power supply voltage and a voltage of thedata line DL0 is a power supply voltage, a voltage of the data line DL0may be maintained. At the same time, since a current path is formed atthe reference data line DLref0, a voltage of the reference data lineDLref0 may lower. Accordingly, during the develop period t2, a voltageof the reference data line DLref0 may be lower than that of the dataline DL0. That is, a difference Vdiff of a voltage of the reference dataline DLref0 minus a voltage of the data line DL0 may be a negativevoltage.

The develop period t2 may be a period where a reference voltage of thereference data line DLref0 is discharged along a given, desired orpredetermined slope. Herein, a value of the given, desired orpredetermined slope may be larger than that of a falling slope of avoltage of the data line DL0. In this case, a current path generator 142may be a kind of discharge circuit.

During the sense period t3, the second latch address LA<1> and the firstcolumn address YA<0> may maintain a high level, and the data sensesignal DSS may have a high level. The differential sense amplifier 143may sense a voltage difference Vdiff between the reference data lineDLref0 and the data line DL0 in response to a high level of the datasense signal DSS. At this time, since the voltage difference Vdiff is anegative voltage, a voltage (e.g., a power supply voltage) correspondingto data ‘0’ may be output to the data node DN.

By the data output method of the nonvolatile memory device according toan example embodiment of inventive concepts, it is possible to rapidlysense data according to whether a voltage difference Vdiff between thereference data line DLref0 and the data line DL0 is a positive voltageor a negative voltage.

The data output method in FIG. 10 may include pre-charging the referencedata line DLref0 and the data line DL0. However, it is well understoodthat pre-charging of the data lines DLref0 and DL0 may be excluded fromthe data output method according to an example embodiment of inventiveconcepts. In inventive concepts, it is possible to sense and output datawithout pre-charging of the data lines DLref0 and DL0. For example, whena voltage of a data line increases due to output data, the data outputmethod may be implemented such that a rising slope of a voltage of thereference data line DLref0 may become slower than that of the data lineDL0. Accordingly, data transferred to a data line may be sensed andoutput during a sensing operation. Afterwards, a reference data line anda data line may be discharged for a data output of a next cycle.

FIG. 11 is a diagram illustrating an output operation of a nonvolatilememory device in FIG. 1 according to another example embodiment ofinventive concepts.

Referring to FIG. 11, an output operation may be divided into a dataoutput operation associated with an even bit line and a data outputoperation associated with an odd bit line as compared with an outputoperation illustrated in FIG. 4. For example, the data output operationmay include connecting an even bit line to a corresponding page bufferlatch in response to an even bit line selection signal BLSe orconnecting an odd bit line to a corresponding page buffer latch inresponse to an odd bit line selection signal BLSo. The output operationin FIG. 11 may be similar or substantially similar to that described inFIGS. 6 to 10 except for the above-described difference.

As illustrated in FIG. 11, a page buffer latch CLAT of each page buffermay be connected with an even bit line and an odd bit line. However, thepage buffers are not limited thereto. Each page buffer may be configuredto include a page buffer latch for an even bit line and a page bufferlatch for an odd bit line.

FIG. 12 is a diagram illustrating an output operation of a nonvolatilememory device in FIG. 1 according to still another example embodiment ofinventive concepts.

Referring to FIG. 12, each page buffer may include the first page bufferlatch CLAT1 for an even bit line and the second page buffer latch CLAT2for an odd bit line. For example, a data output operation may includeconnecting an even bit line to the first page buffer latch CLAT1 inresponse to an even bit line selection signal BLSe or connecting an oddbit line to the second page buffer latch CLAT2 in response to an odd bitline selection signal BLSo. The output operation in FIG. 12 may besimilar or substantially similar to that described in FIGS. 6 to 10except for the above-described difference.

FIG. 13 is a flowchart illustrating a data output method of anonvolatile memory device according to an example embodiment ofinventive concepts. Below, a data output method of a nonvolatile memorydevice will be more fully described with reference to FIGS. 1 to 13.

During a data output operation (or, a read operation), data of memorycells connected with a selected word line selected may be latched bypage buffer latches of page buffers via corresponding bit lines BL. Thismay be performed in operation S110.

Voltages corresponding to data latched at the page buffer latches may betransferred to sub data lines SDL in response to latch addresses LA<0>,LA<1>, etc. The sub data lines SDL may be connected with a data line DLin response to column addresses YA. Thus, data stored in the page bufferlatches is transferred to the data line DL. This may be performed inoperation S120.

In operation S130, a voltage difference between a reference data lineDLref and the data line DL may be sensed in response to a data sensesignal DSS. Herein, during a sensing operation, a current path may beformed at the reference data line DLref. The sensed data may be bufferedand output to an external device.

In case of the data output method according to an example embodiment ofinventive concepts, data may be output rapidly by connecting a data lineDL with page buffers which data is latched at and sensing a voltagedifference between a reference data line DLref and the data line DL.

A nonvolatile memory device according to an example embodiment ofinventive concepts may be configured to randomize input data beforestoring of the input data and to de-randomize stored data beforeoutputting of the stored data.

FIG. 14 is a diagram illustrating a nonvolatile memory device accordingto another example embodiment of inventive concepts.

Referring to FIG. 14, a nonvolatile memory device 200 may furtherinclude a randomizing circuit 235 as compared with that 100 in FIG. 1.The randomizing circuit 235 may be configured to randomize data inputfrom an input/output buffer 240 during an input operation and tode-randomize data provided from a sense amplification circuit 140 duringan output operation. The nonvolatile memory device 200 in FIG. 14 may bethe same or substantially the same as that in FIG. 1 except for theabove-described difference.

Detailed description of an example of the randomizing circuit 245 isdisclosed in U.S. Patent Publication Nos. 2010/0229001, 2010/0229007,and 2010/0259983, the entirety of each of which is incorporated hereinby reference.

The reliability of data may be improved by randomizing data at datainput/output.

A sense amplification circuit according to an example embodiment ofinventive concepts is applicable to, for example, a single data rate(SDR) or double data rate (DDR) NAND flash memory. The SDR NAND flashmemory is disclosed at, for example, (http://onfi.org/specifications/),the entirety of which is incorporated herein by reference. Further, theDDR NAND flash memory is disclosed at(http://www.samsung.com/global/business/semiconductor/products/flash/Products_Toggle_D DR_NANDFlash.html), theentirety of which is incorporated herein by reference.

A nonvolatile memory device according to an example embodiment ofinventive concepts may be configured to selectively use one of asingle-ended transfer mode suitable for the SDR NAND flash memory and adifferential transfer mode suitable for the DDR NAND flash memory duringa data input/output operation.

FIG. 15 is a diagram illustrating a nonvolatile memory device accordingto still another example embodiment of inventive concepts.

Referring to FIG. 15, a nonvolatile memory device 300 may include amemory cell array 110, a page buffer circuit 120, a column selectioncircuit 130, a sense amplification circuit 140, an input/output buffer350, and a transmission mode selector 360. The memory cell array 110,the page buffer circuit 120, the column selection circuit 130, and thesense amplification circuit 140 may be configured the same orsubstantially the same as those in FIG. 1.

The input/output buffer 350 may receive data output from the senseamplification circuit 140 to output the data to an external device. Theinput/output buffer 350 may receive data from the external device tooutput the data to data lines DL. The input/output buffer 350 mayinclude a single-ended input/output buffer 351 and a differentialinput/output buffer 352.

The single-ended input/output buffer 351 may input and output data in asingle-ended transmission mode in response to the first transmissionmode selection signal.

The differential input/output buffer 352 may input and output data in adifferential transmission mode in response to the second transmissionmode selection signal.

The transmission mode selector 360 may be configured to generate thefirst and second transmission mode selection signals. In an exampleembodiment, the transmission mode selector 360 may be configured togenerate the first and second transmission mode selection signalsaccording to configuration of a user or an e-fuse (or, register).

An example data input/output operation executed using any one of thesingle-ended transmission mode and the differential transmission mode isdisclosed in U.S. Patent Publication No. 2008/0273623, the entirety ofwhich is incorporated herein by reference.

The nonvolatile memory device 300 according to an example embodiment ofinventive concepts may be implemented to use the single-endedtransmission mode and the differential transmission mode during datainput/output.

Inventive concepts are also applicable to vertical semiconductor memorydevices (or, called a 3D semiconductor memory devices or VNANDs).

FIG. 16 is a diagram showing a non-volatile memory device according tostill another example embodiment of inventive concepts.

Referring to FIG. 16, a non-volatile memory device 400 may include amemory cell array 410, a driver 420, an input/output circuit 430, andcontrol logic 440.

The memory cell array 410 may include a plurality of memory blocks BLK1to BLKz, each of which includes a plurality of memory cells. Each of thememory blocks BLK1 to BLKz may have a vertical structure (or, athree-dimensional structure).

In this example embodiment, each of the memory blocks BLK1 to BLKz mayinclude structures extending along the first to third directions. Inthis example embodiment, further, each of the memory blocks BLK1 to BLKzmay include a plurality of vertical strings NS extending along thesecond direction. In this example embodiment, each of the memory blocksBLK1 to BLKz may further include a plurality of vertical strings NSextending along the first and third directions. Herein, the first tothird directions may be orthogonal to each other.

Each of the vertical strings NS may be connected to one bit line BL, atleast one string selection line SSL, at least one ground selection lineGSL, word lines WL, and a common source line CSL. That is, each of thememory blocks BLK1 to BLKz may be connected to a plurality of bit linesBL, a plurality of string selection lines SSL, a plurality of groundselection lines GSL, a plurality of word lines WL, and a plurality ofcommon source lines CSL.

The driver 420 may be connected to the memory cell array 410 via aplurality of word lines WL. The driver 420 may be configured to operatein response to the control of the control logic 440. The driver 420 mayreceive an address ADDR from an external device.

The driver 420 may be configured to decode the input address ADDR. Usingthe decoded address, the driver 420 may select one of the plurality ofword lines WL. The driver 420 may be configured to apply voltages toselected and unselected word lines. In an example embodiment, during aprogram operation, a read operation and/or an erase operation, thedriver 420 may supply word lines WL with a program voltage related tothe program operation, a read voltage related to the read operation,and/or an erase voltage related to the erase operation. The driver 420may include a word line driver 421, a selection line driver 422, and acommon source line driver 423.

The input/output circuit 430 may be connected to the memory cell array410 via a plurality of bit lines BL. The input/output circuit 430 mayoperate in response to the control of the control logic 440. Theinput/output circuit 430 may be configured to select a plurality of bitlines BL.

In an example embodiment, the input/output circuit 430 may receive datafrom an external device, randomize the input data, and store therandomized data in the memory cell array 410. The input/output circuit430 may read data from the memory cell array 410, de-randomize or bypassthe read data, and transfer the data to the external device.

The input/output circuit 430 may read data from the first storage regionof the memory cell array 410 to store the data in the second storageregion thereof. In an example embodiment, the input/output circuit 430may be configured to perform a copy-back operation.

In an example embodiment, the input/output circuit 430 may includeconstituent elements such as a page buffer (or, a page register), acolumn selector circuit, a data buffer, and the like. In another exampleembodiment, the input/output circuit 430 may include constituentelements such as a sense amplifier, a write driver, a column selectorcircuit, a data buffer, and the like.

The control logic 440 may be configured to control an overall operationof the non-volatile memory device 400. The control logic 440 may operateresponsive to control signals CTRL transferred from the external device.

Example vertical-type semiconductor memory devices are disclosed in U.S.Patent Publication Nos. 2009/0306583, 2010/0078701, 2010/0117141,2010/0140685, 2010/0213527, 2010/0224929, 2010/0315875, 2010/0322000,2011/0013458, and 2011/0018036, the entirety of all of which isincorporated herein by reference.

FIG. 17 is a circuit diagram showing an equivalent circuit of one memoryblock of memory blocks illustrated in FIG. 16.

Referring to FIGS. 16 and 17, vertical strings NS11 to NS31 may existbetween the first bit line BL1 and a common source line CSL. The firstbit line BL1 may correspond to a conductive material extending in thethird direction. Vertical strings NS12 to NS32 may exist between thesecond bit line BL2 and the common source line CSL. The second bit lineBL2 may correspond to a conductive material extending in the thirddirection. Vertical strings NS13 to NS33 may exist between the third bitline BL3 and the common source line CSL. The third bit line BL3 maycorrespond to a conductive material extending in the third direction.

A string selection transistor SST in each vertical string NS may beconnected to a corresponding bit line BL. A ground selection transistorGST in each vertical string NS may be connected to a common source lineCSL. Memory cells MC may exist between the string selection transistorSST and the ground selection transistor GST in each vertical string NS.

Below, vertical strings NS may be defined by a row unit and a columnunit. Vertical strings NS connected in common to one bit line may form acolumn. In an example embodiment, vertical strings NS11 to NS31connected in common to a first bit line BL1 may correspond to the firstcolumn. Vertical strings NS21 to NS23 connected in common to the secondbit line BL2 may correspond to the second column. Vertical strings NS13to NS33 connected in common to the third bit line BL3 may correspond tothe third column.

Vertical strings NS connected with one string selection line SSL mayform one row. In an example embodiment, vertical strings NS11 to NS13connected with the first string selection line SSL1 may form the firstrow. Vertical strings NS21 to NS23 connected with the second stringselection line SSL2 may form the second row. Vertical strings NS31 toNS33 connected with the third string selection line SSL3 may form thethird row.

In each vertical string NS, a height may be defined. In an exampleembodiment, in each vertical string, a height of a memory cell adjacentto a ground selection transistor GST may be about 1. In each verticalstring NS, a height of a memory cell may increase in inverse proportionto a distance from a string selection transistor SST. In each verticalstring, a height of a memory cell adjacent to the string selectiontransistor SST may be about 7.

Vertical strings NS in the same row may share a string selection lineSSL. Vertical strings NS in different rows may be connected withdifferent string selection lines SSL. In vertical strings of the samerow, memory cells of the same or substantially the same height may sharea word line. At the same or substantially the same height, word lines WLof vertical strings NS of different rows may be connected in common. Inan example embodiment, word lines WL may be connected in common at alayer where conductive materials extending in a first direction areprovided. In an example embodiment, the conductive materials extendingin the first direction may be connected with an upper layer via acontact. Conductive materials extending in the first direction at theupper layer may be connected in common.

Vertical strings NS in the same row may share a ground selection lineGSL.

Vertical strings NS of different rows may be connected with differentground selection lines GSL.

A common source line CSL may be connected in common with verticalstrings NS. In an example embodiment, the first to fourth doping regionsmay be connected at an active region of a substrate. In an exampleembodiment, the first to fourth doping regions may be connected with anupper layer via a contact. The first to fourth doping regions may beconnected in common at the upper layer.

As illustrated in FIG. 17, word lines WL of the same or substantiallythe same depth may be connected in common. Accordingly, when a specificword line WL is selected, all vertical strings NS connected with thespecific word line WL may be selected. Vertical strings NS of differentrows may be connected with different string selection lines SSL.Accordingly, by selecting string selection lines SSL1 to SSL3, verticalstrings of an unselected row among vertical strings NS connected withthe same word line WL may be separated from bit lines BL1 to BL3. Thatis, a row of vertical strings NS may be selected by selecting stringselection lines SSL1 to SSL3. Vertical strings NS of a selected row maybe selected by a column unit by selecting the bit lines BL1 to BL3.

In FIGS. 1 to 17, an example sense amplification circuit is describedusing a nonvolatile memory device. However, it is well understood thatthere is no need to limit the sense amplification circuit to thenonvolatile memory device. The sense amplification circuit according toan example embodiment of inventive concepts is applicable to a volatilememory device.

FIGS. 18 to 25 show applications of a nonvolatile memory deviceaccording to an example embodiment of inventive concepts.

FIG. 18 is a diagram illustrating a memory system according to anexample embodiment of inventive concepts.

Referring to FIG. 18, a memory system 1000 may include a non-volatilememory device 1100 and a memory controller 1200.

The nonvolatile memory device 1100 may be implemented in the same orsubstantially the same manner as a non-volatile memory device 100 ofFIG. 1, a non-volatile memory device 300 of FIG. 15, or a non-volatilememory device 400 of FIG. 16.

The memory controller 1200 may include at least one Central ProcessingUnit (CPU) 1210, a buffer 1220, an Error Correction Circuit (ECC) 1230,a Read-Only Memory (ROM) 1240, a host interface 1250, and a memoryinterface 1260. The memory system 1000 according to an exampleembodiment of inventive concepts is applicable to a perfect page new(PPN) memory.

Detailed description of an example memory system is disclosed in U.S.Patent Publication No. 2010/0082890, the entirety of which isincorporated herein by reference.

FIG. 19 is a block diagram of a memory card according to an exampleembodiment of inventive concepts.

Referring to FIG. 19, a memory card 2000 may include at least one flashmemory 2100, a buffer memory 2200, and a memory controller 2300 forcontrolling the flash memory 2100 and the buffer memory 2200.

The flash memory device 2100 may be implemented in the same orsubstantially the same manner as a non-volatile memory device 100 ofFIG. 1, a non-volatile memory device 300 of FIG. 15, or a non-volatilememory device 400 of FIG. 16.

The buffer memory device 2200 may be used to temporarily store datagenerated during the operation of the memory card 2000. The buffermemory device 2200 may be implemented using a dynamic random accessmemory (DRAM) or a static random access memory (SRAM).

The memory controller 2300 may be connected between a host and the flashmemory 2100. The memory controller 2300 may be configured to access theflash memory 2100 in response to a request from the host.

The memory controller 2300 may include at least one microprocessor 2310,a host interface 2320, and a flash interface 2330.

The microprocessor 2310 may be configured to drive firmware. The hostinterface 2320 may interface with the host via a card (e.g., MMC)protocol for data exchanges between the host and the memory interface2330.

The memory card 2000 may be applicable to Multimedia Cards (MMCs),Security Digitals (SDs), miniSDs, memory sticks, smartmedia, transflashcards, etc.

A detailed description of an example memory card 2000 is disclosed inU.S. Patent Publication No. 2010/0306583, the entirety of which isincorporated herein by reference.

FIG. 20 is a block diagram of a moviNAND according to an exampleembodiment of inventive concepts.

Referring to FIG. 20, a moviNAND device 3000 may include a NAND flashmemory device 3100 and a controller 3200. The moviNAND device 3000 maysupport the MMC 4.4 (called eMMC) standard.

The NAND flash memory device 3100 may be formed by a stack of unitaryNAND flash memories in a package (e.g., Fine-pitch Ball Grid Array(FBGA)). The unitary NAND flash memory device may be implemented in thesame or substantially the same manner as a non-volatile memory device100 of FIG. 1, a non-volatile memory device 300 of FIG. 15, or anon-volatile memory device 400 of FIG. 16.

The controller 3200 may include at least one controller core 3210, ahost interface 3220, and a NAND interface 3230. The controller core 3210may control an overall operation of the moviNAND device 3000. The hostinterface 3220 may be configured to perform an MMC interface between thecontroller 3210 and a host. The NAND interface 3230 may be configured tointerface between the NAND flash memory device 3100 and the controller3200.

The moviNAND device 3000 may receive power supply voltages Vcc and Vccqfrom the host. Herein, the power supply voltage Vcc (about 3V) may besupplied to the NAND flash memory device 3100 and the NAND interface3230, while the power supply voltage Vccq (about 1.8V/3V) is supplied tothe controller 3200.

The moviNAND 300 according to an example embodiment of inventiveconcepts may be advantageous in storing mass data as well as havingimproved read characteristics. The moviNAND 3000 according to an exampleembodiment of inventive concepts is applicable to relatively small andlow-power mobile products (e.g., smartphones, such as, a Galaxy S,iPhone, etc).

Inventive concepts are also applicable to a solid state drive (SSD).

FIG. 21 is a block diagram of an SSD according to an example embodimentof inventive concepts.

Referring to FIG. 21, an SSD 4000 may include a plurality of flashmemory devices 4100 and an SSD controller 4200. Each of the flash memorydevices 4100 may be implemented in the same or substantially the samemanner as a non-volatile memory device 100 of FIG. 1, a non-volatilememory device 300 of FIG. 15, or a non-volatile memory device 400 ofFIG. 16.

The SSD controller 4200 may control the plurality of flash memorydevices 4100. The SSD controller 4200 may include at least one CPU 4210,a host interface 4220, a buffer 4230, and a flash interface 4240.

Under the control of the CPU 4210, the host interface 4220 may exchangedata with a host through the ATA protocol. The host interface 4220 maybe one of a Serial Advanced Technology Attachment (SATA) interface, aParallel Advanced Technology Attachment (PATA) interface, and anExternal SATA (ESATA) interface. Data to be received or transmitted fromor to the host through the host interface 4220 may be delivered throughthe buffer 4230 without passing through a CPU bus, under the control ofthe CPU 4210.

The buffer 4230 may temporarily store data transferred between anexternal device and the flash memory devices 4100. The buffer 4230 maybe used to store programs to be executed by the CPU 4210. The buffer4230 may be implemented using a SRAM. The buffer 4230 in FIG. 21 may beincluded within the SSD controller 4200. However, the inventive conceptsare not limited thereto. The buffer 4230 according to an exampleembodiment of inventive concepts may be provided at an outside of theSSD controller 4200.

The flash interface 4240 may be configured to interface between the SSDcontroller 4200 and the flash memory devices 4100 that are used asstorage devices. The flash interface 4240 may be configured to supportNAND flash memories, One-NAND flash memories, multi-level flashmemories, or single-level flash memories.

The SSD 4000 according to an example embodiment of inventive conceptsmay improve the reliability of stored data by storing random data duringa program operation. A more detailed description of an example of theSSD 4000 is disclosed in U.S. Patent Publication No. 2010/0082890, theentirety of which is incorporated herein by reference.

FIG. 22 is a block diagram of a computing system including an SSD inFIG. 21 according to an example embodiment of inventive concepts.

Referring to FIG. 22, a computing system 5000 may include at least oneCPU 5100, a ROM 5200, a RAM 5300, an input/output (I/O) device 5400, andat least one SSD 5500.

The at least one CPU 5100 may be connected to a system bus. The ROM 5200may store data used to drive the computing system 5000. Herein, the datamay include a start command sequence or a basic I/O system (BIOS)sequence. The RAM 5300 may temporarily store data generated during theexecution of the CPU 5100.

The I/O device 5400 may be connected to the system bus through an I/Odevice interface such as keyboards, pointing devices (e.g., mouse),monitors, modems, and the like.

The SSD 5500 may be a readable storage device and may be implemented inthe same or substantially the same manner as the SSD 4000 of FIG. 11.

FIG. 23 is a block diagram of an electronic device including an SSD inFIG. 21 according to an example embodiment of inventive concepts.

Referring to FIG. 23, an electronic device 6000 may include at least oneprocessor 6100, a ROM 6200, a RAM 6300, a flash interface 6400, and anSSD 6500.

The at least one processor 6100 may access the RAM 6300 to executefirmware codes or other codes. Also, the processor 6100 may access theROM 6200 to execute fixed command sequences such as a start commandsequence and a basic I/O system (BIOS) sequence. The flash interface6400 may be configured to interface between the electronic device 6000and the SSD 6500. The SSD 6500 may be detachable from the electronicdevice 6000. The SSD 6500 may be implemented the same as the SSD 4000 ofFIG. 21.

The electronic device 6000 may include cellular phones, personal digitalassistants (PDAs), digital cameras, camcorders, portable audio players(e.g., MP3), portable media players (PMPs), etc.

FIG. 24 is a block diagram of a server system including an SSD in FIG.21 according to an example embodiment of inventive concepts.

Referring to FIG. 24, a server system 7000 may include at least oneserver 7100 and an SSD 7200 that stores data used to drive the server7100. The SSD 7200 may be configured in the same or substantially thesame manner as an SSD 4000 of FIG. 21.

The server 7100 may include an application communication module 7110, adata processing module 7120, an upgrade module 7130, a scheduling center7140, a local resource module 7150, and a repair information module7160.

The application communication module 7110 may be configured tocommunicate with a computing system connected to a network and theserver 7100, or to allow the server 7100 to communicate with the SSD7200. The application communication module 7110 may transmit data orinformation, provided through a user interface, to the data processingmodule 7120.

The data processing module 7120 may be linked to the local resourcemodule 7150. Here, the local resource module 7150 may provide a list ofrepair shops/dealers/technical information to a user on the basis ofinformation or data inputted to the server 7100.

The upgrade module 7130 may interface with the data processing module7120. Based on information or data received from the SSD 7200, theupgrade module 7130 may perform upgrades of a firmware, a reset code, adiagnosis system, or other information on electronic appliances.

The scheduling center 7140 may provide real-time options to the userbased on the information or data inputted to the server 7100.

The repair information module 7160 may interface with the dataprocessing module 7120. The repair information module 7160 may be usedto provide repair-related information (e.g., audio, video or documentfiles) to the user. The data processing module 7120 may packageinformation related to the information received from the SSD 7200. Thepackaged information may be transmitted to the SSD 7200 or may bedisplayed to the user.

A non-volatile memory device according to an example embodiment ofinventive concepts is applicable to tablet products (e.g., Galaxy Tab,iPad, etc.).

FIG. 25 is a diagram showing a handheld electronic device according toan example embodiment of inventive concepts.

Referring to FIG. 25, a handheld electronic device 8000 may include atleast one computer-readable media 8020, a processing system 8040, aninput/output sub-system 8060, a radio frequency circuit 8080, and anaudio circuit 8100. Respective constituent elements may beinterconnected by at least one communication bus or a signal line 8030.

The handheld electronic device 8000 may be any handheld electronicdevice including a handheld computer, a tablet computer, a mobile phone,a media player, a PDA, or a combination of at least two elementsthereof. Herein, the at least one computer-readable media 8020 includesat least one non-volatile memory device 100 in FIG. 1. A more detaileddescription of an example of the handheld electronic device 800 isdisclosed in U.S. Pat. No. 7,509,588, the entirety of which isincorporated herein by reference.

Memory systems or storage devices according to example embodiments ofinventive concepts may be mounted in various types of packages. Examplesof the packages of the memory system or the storage device according toexample embodiments of inventive concepts may include Package on Package(PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), PlasticLeaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Die inWaffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic DualIn-line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), ThinQuad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), ShrinkSmall Outline Package (SSOP), Thin Small Outline Package (TSOP), SystemIn Package (SIP), Multi Chip Package (MCP), Wafer-level FabricatedPackage (WFP), and Wafer-level Processed Stack Package (WSP).

Nonvolatile memory devices according to example embodiments of inventiveconcepts may perform a high-speed data output operation by outputtingdata according to a differential sensing method. Further, nonvolatilememory devices according to example embodiment of inventive concepts mayreduce a layout area by differentially sensing data lines andcorresponding reference data lines.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope. Thus, to the maximum extent allowed by law,the scope is to be determined by the broadest permissible interpretationof the following claims and their equivalents, and shall not berestricted or limited by the foregoing detailed description.

What is claimed is:
 1. An output circuit comprising: a plurality of pagebuffer latches configured to latch data read from a plurality of memorycells; a plurality of sub data lines configured to receive voltagescorresponding to the latched data in response to latch addresses; a dataline connected to the plurality of sub data lines; a reference data lineto which a current path is formed during a sensing operation; and asense amplification circuit configured to, during the sensing operation,sense a voltage difference between the reference data line and the dataline, and to output data corresponding to the sensed voltage difference.